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Empyrean Ada™ – Layout Parasitic Analysis

Fast DSPF Based RC Analysis

Shrinking process geometries along with the use of new device structures and an increasing number of metal layers are introducing new parasitic effects in IC designs. These effects require excessive simulation times to verify the design. To ensure a successful design and tape-out schedule, IC designers need an advanced parasitic analysis and layout solution, that delivers fast, accurate results and increases designer productivity.

Empyrean Ada™ provides high-performance RC analysis for design optimization. Leveraging its large capacity database and multi-threading support and back-annotation capability function with Empyrean Skipper®, Ada provides a fast accurate solution of parasitic analysis for design optimization.  Ada is very user-friendly supporting both batch and GUI operations.

The analysis includes Net RC analysis, Net RC comparison, Node-to-node R analysis, cross-coupling analysis, and Advanced P2PR analysis.

Key Benefits
Quick Optimization to Locate the Critical Nets
 High Performance - Next Gen database and multi-threading support 
 High Efficiency - Quick analysis of parasitic resistance and capacitance
 Ease of Use - Seamless GUI and back-annotation interactive with Aether and Skipper


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