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Empyrean Argus™ – Physical Verification

High-performance Physical Verification Signoff Solution

Empyrean Argus™ is a hierarchical and parallel physical verification tool that meets the requirements of ultra-deep submicron IC designs. It effectively locates design violations, reduces verification time, and improves productivity.

The tool can be seamlessly integrated into Empyrean Aether™, an analog circuit schematic and layout design platform, and Empyrean Skipper®, a massive layout processing platform, and helps layout engineers quickly locate layout design errors, speed up the verification process and shorten the product development cycle through easy-to-use debug functions.

Empyrean Argus™ has gained extensive support from leading foundries worldwide, providing designers with signoff-level verification.


Key Benefits 
Signoff Quality Verification Accuracy
 High Performance – a new generation nanoscale chip hierarchical parallel physical verification

 High Accuracy – layout preprocessing detects and resolves design errors early in the design cycle

         and ensures signoff level accuracy without impacting performance 
 Ease of Use – DRStudio for rules development and rich debug functionality improves usage

         efficiency and productivity

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