High-performance Layout Integration and Chip Analysis

Empyrean Skipper^® provides a powerful layout analysis and integration solution that can greatly improve the efficiency of layout sign-off. Skipper's high performance is powered by an innovative cache mode and share memory mode which reduces layout loading time. Its parallel layout scan technology enables efficient IP merging.  

Empyrean Skipper^® layout data analysis includes net/short tracing and debugging, layout comparison, reliability analysis: P2P, weak connectivity, density checking, and pad report. Skipper also has an easy-to-use LVS/DRC violations review and debugging, FIB processing, and a unique digital signature technology to better manage and track IP data.
 

Key Benefits
Efficient Layout Sign-off
 High Performance – supporting cache and share memory mode for fast layout loading
 Large Capacity Layout Analysis – net/short tracing, LVL, P2P analysis
 Fast IP Merging – using parallel scan technology