Comprehensive Platform for Checking Standard Cell Libraries

Empyrean Qualib® provides a comprehensive platform for standard cell library and IP analysis and validation. It helps designers perform library quality inspections. It also provides the PPA (Performance, Power, and Area) comparison and trend analysis, dynamic timing validation via SPICE simulation, and IP missing arc validation using AI technology. Liberty APIs are supported for detailed and customized timing data verification and analysis.

Empyrean Qualib® supports various library views and design data formats, including GDSII/OASIS, Verilog, Liberty, LEF, etc. It has been successfully applied to various process nodes and design types, such as standard cell library, Memory, IO, and analog IP. With its user-friendly GUI, detailed and complete inspection reports, performance advantages, and advanced analysis capabilities, Qualib® significantly reduces iterations, ensures design quality, and shortens the time to market.

Key Benefits
Fast and Accurate IP Validation
 Accurate Validation – SPICE-powered dynamic validation
 AI-powered – IP missing ARC validation 
 Library PPA Evaluation and Trend Analysis – Standard cell and memory supported