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Layout Reliability Analysis

Empyrean Polas

Simulating the working state of power ICs accurately to improve their reliability and yield is a difficult problem for power IC designers. Traditional RC extraction methods cannot satisfy power IC design needs because power ICs often use special shapes and have large areas. Sometimes their layout satisfies DRC/LVS rules but they still may not function correctly. Often a long time is required to do accurate power and current simulations for power ICs using traditional RC extraction methods and simulators, leading to long analysis and debugging cycles. As a result, it is difficult to predict the performance and reliability of power ICs, which leads to higher design risk and longer product development cycles.

Empyrean Polas is a reliability analysis tool for power IC designs that address the design difficulties mentioned above. Empyrean Polas provides comprehensive capabilities such as Rds(on) calculation, EM/IR-drop analysis, power gate timing analysis, and crosstalk analysis. Empyrean Polas is an effective and one-stop solution for power IC analysis, and it allows designers to sign off and safeguards the quality of their designs.

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