Complete solutions for AMS and PMIC designs

Schematic and Layout Design Environment
Empyrean Aether™ is an analog IC design platform with schematic and layout editing seamlessly integrated with SPICE simulator Empyrean ALPS^®, physical verification tool Empyrean Argus™, parasitic RC extraction tool Empyrean RCExplorer™ and reliability analysis tool Empyrean Polas™.

Simulation and EM/IR
Empyrean ALPS^® is a high-performance parallel SPICE simulator. It’s an ideal solution for large-scale post-layout circuit simulation. Empyrean ALPS^® GT is a heterogeneous SPICE simulator using CPU and GPU for acceleration. It further improves post-layout circuit simulation and helps reduce the design cycle.

Empyrean Patron™ is a transistor-level power integrity analysis tool, which focuses on analog chip power integrity solutions.
 

RC Extraction and Analysis
Empyrean RCExplorer™ supports transistor level and standard cell level post-layout extraction for analog designs. It also supports point-to-point RC analysis and timing delay analysis.

Empyrean ADA™ is a DSPF-based RC analysis tool with cross-referencing layouts.

Physical Verification
Empyrean Argus™ is a physical verification tool that includes DRC and LVS. It can help improve verification quality and efficiency.

PMIC Solutions
Empyrean Polas™ is a layout reliability analysis solution for Power IC design.