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Article originally published on, "Empyrean Technology's Complete Design Solution for PMIC"

Wrote by Daniel Nenni on 11-28-2021 at 6:00 am

Power management integrated circuits (PMICs) are integrated circuits for power managements. Driven by the strong demand in consumer electronics, IoT, and automobile industry, the design for PMIC is getting more challenging in terms of integration, reliability and efficient. The design methodology needs update to handle complex integration within a smaller footprint and higher performance; a better simulation solution for better verification on multi-scenarios; a reliability verification solution to handle high power density.

A power MOSFET with an area of several square millimeters is the core of a PMIC. It's important for those parallel transistors to have a very low on-resistance, or Rds(on). Although PMIC design is still using mature process node, PMIC has becoming highly integrated with digital techniques and blocks like ADC and timer. It makes the verification and optimization of PMIC more challenging and time consuming. Traditional RC extraction methods cannot satisfy power IC design needs because power ICs often use special shapes and have large areas. Sometimes their layout satisfies DRC/LVS rules but they still may not function correctly. Often a long time is required for accurate power and current simulations for power ICs using traditional RC extraction methods and simulators, leading to long analysis and debugging cycles.

Empyrean Technology provides a complete design solution for PMIC that addresses above needs. Empyrean's solution has helped customers worldwide to tape out billions of PMICs over 10 years. Empyrean's solution supports major PMIC processes and has been certified by several major foundries.

Empyrean Aether is a design platform with schematic and layout entry. It can integrate with Empyrean's SPICE simulator, physical verification, and RC extraction tool. supports mature processes from various foundries.

Empyrean ALPS is a high-performance true SPICE simulator. It supports up to the latest processes with optimized engine to provide better convergency on high voltage design. ALPS can greatly improve your design verification performance on cases with multi-corners and long ramp-up time. Being integrated with Aether, ALPS provides GUI-based simulation environment for PVT simulation, circuit check, and result debugging.

Empyrean Argus is a hierarchical parallel physical verification tool. It provides DRC/LVS/Dummy Fill and DFM. Argus supports voltage-dependent DRC. It supports dynamic checks between nets with different power supply voltage. Argus engine can also handle shapes placed in any angle without compromising accuracy.

Empyrean RCExplorer supports transistor-level and gate-level RC extraction. It has built-in field solver that provides high accuracy resistance and capacitance calculation. 

Empyrean Polas provides reliability analysis such as Rds(on) calculation, EM/IR-drop analysis, power MOSFET timing analysis, and crosstalk analysis. It has built-in field solver to handle specials polygons in the layout for accurate extraction. Rds(on) and power path resistance is calculated accurately by SPICE simulation. Gate delay distribution for MOSFETs is calculated by dynamic simulation. High performance SPICE simulation also enables efficient current density analysis for EM effects, and facilitates IR-drop analysis that takes into account contacts, vias and metal layers. You can refer to this article to learn how MPS using Polas for their power MOSFET devices. ( )

Empyrean Technology will showcase at the 58th Design Automation Conference (DAC) in Moscone West in San Francisco, CA from December 5-9, 2021. Empyrean Technology kindly invites you to visit their booth 2537 if you have question or want to know more about their PMIC solution.


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